CVS difference for arm/source/sp.mss

Differences between 1.58 and version 1.59
Log of other versions for file arm/source/sp.mss

--- arm/source/sp.mss	2010/10/15 07:05:38	1.58
+++ arm/source/sp.mss	2010/11/25 03:11:50	1.59
@@ -1,7 +1,7 @@
 @comment{ $Source: e:\\cvsroot/ARM/Source/sp.mss,v $ }
-@comment{ $Revision: 1.58 $ $Date: 2010/10/15 07:05:38 $ $Author: randy $ }
+@comment{ $Revision: 1.59 $ $Date: 2010/11/25 03:11:50 $ $Author: randy $ }
 @Part(sysprog, Root="ada.mss")
-@Comment{$Date: 2010/10/15 07:05:38 $}
+@Comment{$Date: 2010/11/25 03:11:50 $}
 
 @LabeledNormativeAnnex{Systems Programming}
 
@@ -1328,11 +1328,18 @@
 For an atomic object (including an atomic component) all reads and
 updates of the object as a whole are indivisible.
 
-For a volatile object all reads and updates of the
-object as a whole are performed directly to memory.
+@ChgRef{Version=[3],Kind=[Revised],ARef=[AI05-0117-1]}
+@Chg{Version=[3],New=[All tasks of the program (on all processors) that read or update volatile
+variables see the same order of updates to the variables.
+],Old=[For a volatile object all reads and updates of the
+object as a whole are performed directly to memory.]}
+
 @begin{ImplNote}
-This precludes any use of register temporaries, caches, and other
-similar optimizations for that object.
+@ChgRef{Version=[3],Kind=[Revised],ARef=[AI05-0117-1]}
+@Chg{Version=[3],New=[To ensure this, on a multiprocessor, any read or
+update of a volatile object should involve the use of an appropriate memory
+barrier.],Old=[This precludes any use of register temporaries,
+caches, and other similar optimizations for that object.]}
 @end{ImplNote}
 
 @Defn2{Term=[sequential], Sec=(actions)}
@@ -1489,6 +1496,14 @@
   parameters (see @RefSecNum{Subprogram Declarations}) into
   account when determining the legality of parameter passing of volatile and
   atomic objects.]}
+
+  @ChgRef{Version=[3],Kind=[AddedNormal],ARef=[AI05-0117-1]}
+  @ChgAdded{Version=[3],Text=[Revised the definition of volatile to
+  eliminate overspecification and simply focus on the root requirement (that
+  all tasks see the same view of volatile objects). This is not an inconsistency;
+  "memory" arguably includes on-chip caches so long as those are kept
+  consistent. Moreover, it is dificult to imagine a program that could tell
+  the difference.]}
 @end{DiffWord2005}
 
 

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